DVCon 2003 Sponsored by Accellera Feb. 24-26, 2003 DoubleTree Hotel San Jose San Jose, California http://www.dvcon.org ---------------------------------------------------------------- DVCon 2003 is the premier conference on the usage of Hardware Description Languages (HDLs), and Hardware Verification Languages (HVLs)for the design and verification of electronic systems and integrated circuits. Formerly HDLCon, the expanded focus comes as the need for efficient design and verification languages have become extremely critical to semiconductor designs, advancing the growing popularity of assertion-centric verification. This year's conference offers a comprehensive forum to fully explore HDL and HVL solutions to both implement and verify hardware virtual prototypes. CONFERENCE HIGHLIGHTS * 3 panel sessions by industry experts 1- Is Methodology Driving Language, or Vice Versa? 2- Verilog and Assertions - Do they Mix? 3- EDA Directions * Monday Luncheon Keynote, Aart de Geus, Chairman & CEO of Synopsys: Design for Verification: A New Paradigm * Tuesday Luncheon & Presentations: Updates on the SystemC Standard * 7 tutorials presented by industry experts on new tricks in design and verification * 38 papers presented on a wide range of engineering topics TECHNICAL HIGHLIGHTS * SoC Verification with Assertions * Assertion-based Hardware Debugging * Impact of Synthesis on Design Closure - OR - The Netlist Matters! * The Case for Verification Languages * HDL and C/C++ Design Productivity in a Mixed Language Environment * SystemVerilog 3.1, it's what the DAVEs in Your Company asked for * Curing Schizophrenic Tendencies in Multi-Level System Design For a complete agenda, visit: http://www.dvcon.org/techprog.html CONFERENCE REGISTRATION ADVANCE REGISTRATION DEADLINE: MONDAY, FEBRUARY 3, 2003 To register for the conference, you may register on-line, via mail or fax. Full conference registration includes admission to all technical sessions on Monday and Tuesday, the Monday evening cocktail reception, daily coffee service, lunch and a copy of the CD-Rom proceedings HOTEL RESERVATIONS / DEADLINE: THURSDAY, JANUARY 23, 2003 The DVCon discounted room rate of $149 single/double is limited, and we encourage you to make your reservations as soon as possible. Reservations may be made by contacting the hotel directly at 408-453-4000 TUTORIALS, WEDNESDAY, FEBRUARY 26, 2003 Tutorial 1: Practical Verilog for Chip-level Verification Tutorial 2: Functional Verification with Specman Elite, Step-by-Step Tutorial 3: Finding More Bugs with VERA's Constraint-Driven Stimulus Generation Tutorial 4: The Sugar 2.0 Property Specification Language - A Language for All Seasons Tutorial 5: Transaction-based Modeling and Verification with SystemC Tutorial 6: An Introduction to Smart Verification Using SystemVerilog Tutorial 7: The Design Flow - Linking Design, Verification, and Common Sense to Build Chips that Work EXHIBITS In no other venue will you see such a comprehensive and focused offering of HDL tools and solutions. Visit the web site for a complete listing of participating vendors. Be sure to join us at the annual cocktail reception in the Exhibit Hall, sponsored by Mentor Graphics on Monday, February 24th from 5:00pm-7:00pm. Exhibit Hours: Monday, February 24th: 12pm-7pm Tuesday, February 25th: 9am-12pm We look forward to seeing you at DVCon 2003, February 24-26, 2003 at the DoubleTree Hotel San Jose. *************************************************************************************************************************************** This is the list for the Accellera Member Announcements. You have been subscribed to this list if you have either requested Accellera membership or attended a Accellera sponsored conference. This list is used to send periodic announcements on upcoming events and other useful information. If you would like to remove yourself from this list, please click: http://mpassociates.post.intellimedia.com/UM/U.asp?B1031.12346.128.10274 and you will be removed immediately! Thank you!